1. Field of the Invention
The present invention generally relates to data communications and, more particularly, to signal processing for clock recovery and data re-timing in data link equipment operating in a receiver mode.
2. Description of the Related Art
Data communications is concerned with the movement and exchange of encoded information--a set or block of one or more encoded (e.g. digitally) alphabetic and numerical characters--between any two data terminal equipments (DTEs) in a communications link. One critical element to the reliable and efficient exchange of information is the correct timing synchronization of the transmitter and receiver.
In order for the receiving device to decode and interpret the incoming bit pattern on a communication link correctly, one of the flow parameters which it is necessary for the receiver to know is the bit rate being used, i.e., the time duration of each bit period. This is known as bit or clock synchronism. Hence, within each DTE there must be transmission control circuits--also known as communication interface circuits--which couple the device to the data link and which include timing synchronization among their functions. Retiming is also used to erase jitter caused by intersymbol interference and other link deficiencies.
Synchronism is accomplished in one of two ways which are determined by whether a transmitted and receiver clocks are independent (asynchronous) or synchronized (synchronous). In asynchronous transmission, data are generated at random intervals and start and stop bits are used for each character envelope in order to establish synchronism. In synchronous transmission, however, start and stop bits are not used. Instead, each frame is transmitted as a continuous stream of binary digits. A common method of synchronization is to have the information to be transmitted encoded in such a way that there are sufficient guaranteed transitions in the transmitted bit stream to resynchronize the receiver clock at frequent intervals.
The frequency spectrum of data transmitted in common, bandwidth-efficient, non-return to zero (NRZ) format has zero power at the bit-rate frequency. As known in the art, to recover the clock from an NRZ data stream, the data must be first quasi-differentiated and then submitted to full-wave rectification by the receiver communications interface circuits. A typical circuit is shown in FIG. 1; the corresponding waveform generation is shown in FIG. 2.
Referring to the FIGURES, waveform A represents an incoming, bandwidth limited, arbitrary NRZ data stream with a bit period of T on communication link 2. Waveform B is the same data stream after quasi-differentiation resulting in pulses of width d on interconnection line 4. Waveform C on line 6 is the pulse waveform B following full wave rectification; the spectrum of waveform C has a strong component at the clock frequency. Waveform C is processed through a phase locked loop circuit to produce a recovered, synchronized clock waveform D on line 8 as the clock pulse for sampling the input data A at the input flip-flop 11. A voltage controlled oscillator (receiver source clock) having a frequency equal to the bit rate being used on the data link is used by the phase locked loop circuit to derive the timing interval between successive samples of the received bit stream. By successive adjustments, the loop keeps the generated sampling transitions of clock pulses D close to the approximate center of each bit period.
As a result of the signal processing by the communication interface circuit described above, waveform E on line 10 is the input signal A retimed by sampling the incoming data stream A by the recovered clock pulse D.
This common technique is not without its drawbacks. In order to guarantee optimum sampling (vis., near the center of the bit period T) of the incoming data A by the clock pulse D, the recovered clock D must be in a specific phase relation with the incoming data A. However, the phase of the clock component recovered by the phase locked loop will be a strong function of the ratio of pulse width d in waveforms B and C to the bit period T.
If by operating the data link at different data rates the bit period T significantly changes, pulse width d must be changed proportionally to T in order to maintain proper sampling of bit stream A at the D flip flop. This is usually done by changing a component (such as a capacitor used to set the width d of the pulses of waveform C) in the quasi-differentiation circuit whenever changing the link data rate.
Hence, such prior art systems require complex changes when the bit rate is changed.